[rtl, gpio] Refactor gpio declaration by engdoreis · Pull Request #452 · lowRISC/sonata-system

engdoreis · 2025-09-26T14:53:40Z

The gpio was as declared in some places as having a single instance, but in other places it has 6 instances. This commit makes it consistent.

This change expand the number of instances of the GPIO block connected to the xbar.

This is the bitstream build report for these changes:

+----------------------------+-------+-------+------------+-----------+-------+
|          Site Type         |  Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs                 | 26385 |     0 |          0 |     32600 | 80.94 |
|   LUT as Logic             | 26287 |     0 |          0 |     32600 | 80.63 |
|   LUT as Memory            |    98 |     0 |          0 |      9600 |  1.02 |
|     LUT as Distributed RAM |    98 |     0 |            |           |       |
|     LUT as Shift Register  |     0 |     0 |            |           |       |
| Slice Registers            | 16493 |     0 |          0 |     65200 | 25.30 |
|   Register as Flip Flop    | 16493 |     0 |          0 |     65200 | 25.30 |
|   Register as Latch        |     0 |     0 |          0 |     65200 |  0.00 |
| F7 Muxes                   |   597 |     0 |          0 |     16300 |  3.66 |
| F8 Muxes                   |   146 |     0 |          0 |      8150 |  1.79 |
+----------------------------+-------+-------+------------+-----------+-------+

+--------------------------------------------+-------+-------+------------+-----------+-------+
|                  Site Type                 |  Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Slice                                      |  7790 |     0 |          0 |      8150 | 95.58 |
|   SLICEL                                   |  5490 |     0 |            |           |       |
|   SLICEM                                   |  2300 |     0 |            |           |       |
| LUT as Logic                               | 26287 |     0 |          0 |     32600 | 80.63 |
|   using O5 output only                     |     1 |       |            |           |       |
|   using O6 output only                     | 20925 |       |            |           |       |
|   using O5 and O6                          |  5361 |       |            |           |       |
| LUT as Memory                              |    98 |     0 |          0 |      9600 |  1.02 |
|   LUT as Distributed RAM                   |    98 |     0 |            |           |       |
|     using O5 output only                   |     0 |       |            |           |       |
|     using O6 output only                   |    26 |       |            |           |       |
|     using O5 and O6                        |    72 |       |            |           |       |
|   LUT as Shift Register                    |     0 |     0 |            |           |       |
| Slice Registers                            | 16493 |     0 |          0 |     65200 | 25.30 |
|   Register driven from within the Slice    |  7300 |       |            |           |       |
|   Register driven from outside the Slice   |  9193 |       |            |           |       |
|     LUT in front of the register is unused |  2675 |       |            |           |       |
|     LUT in front of the register is used   |  6518 |       |            |           |       |
| Unique Control Sets                        |  1013 |       |          0 |      8150 | 12.43 |
+--------------------------------------------+-------+-------+------------+-----------+-------+

This is the same report from build on the main branch:

+----------------------------+-------+-------+------------+-----------+-------+
|          Site Type         |  Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs                 | 26084 |     0 |          0 |     32600 | 80.01 |
|   LUT as Logic             | 25986 |     0 |          0 |     32600 | 79.71 |
|   LUT as Memory            |    98 |     0 |          0 |      9600 |  1.02 |
|     LUT as Distributed RAM |    98 |     0 |            |           |       |
|     LUT as Shift Register  |     0 |     0 |            |           |       |
| Slice Registers            | 16212 |     0 |          0 |     65200 | 24.87 |
|   Register as Flip Flop    | 16212 |     0 |          0 |     65200 | 24.87 |
|   Register as Latch        |     0 |     0 |          0 |     65200 |  0.00 |
| F7 Muxes                   |   492 |     0 |          0 |     16300 |  3.02 |
| F8 Muxes                   |   141 |     0 |          0 |      8150 |  1.73 |
+----------------------------+-------+-------+------------+-----------+-------+

+--------------------------------------------+-------+-------+------------+-----------+-------+
|                  Site Type                 |  Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Slice                                      |  7803 |     0 |          0 |      8150 | 95.74 |
|   SLICEL                                   |  5504 |     0 |            |           |       |
|   SLICEM                                   |  2299 |     0 |            |           |       |
| LUT as Logic                               | 25986 |     0 |          0 |     32600 | 79.71 |
|   using O5 output only                     |     1 |       |            |           |       |
|   using O6 output only                     | 20821 |       |            |           |       |
|   using O5 and O6                          |  5164 |       |            |           |       |
| LUT as Memory                              |    98 |     0 |          0 |      9600 |  1.02 |
|   LUT as Distributed RAM                   |    98 |     0 |            |           |       |
|     using O5 output only                   |     0 |       |            |           |       |
|     using O6 output only                   |    26 |       |            |           |       |
|     using O5 and O6                        |    72 |       |            |           |       |
|   LUT as Shift Register                    |     0 |     0 |            |           |       |
| Slice Registers                            | 16212 |     0 |          0 |     65200 | 24.87 |
|   Register driven from within the Slice    |  7209 |       |            |           |       |
|   Register driven from outside the Slice   |  9003 |       |            |           |       |
|     LUT in front of the register is unused |  2866 |       |            |           |       |
|     LUT in front of the register is used   |  6137 |       |            |           |       |
| Unique Control Sets                        |   992 |       |          0 |      8150 | 12.17 |
+--------------------------------------------+-------+-------+------------+-----------+-------+

elliotb-lowrisc

Some initial comments. I'd also be interested in seeing if the addition of more tlul_adapter_reg's in gpio.sv has affected the FPGA timing or area

elliotb-lowrisc · 2025-09-26T15:21:31Z

data/xbar_main.hjson

+      "gpio0",
+      "gpio1",
+      "gpio2",
+      "gpio3",
+      "gpio4",
+      "gpio5",


Would you be able to move these back up to where the single gpio was before? These are roughly in order of address.

I was trying to make it to follow the same rules as uart, spi and i2c where every instance is listed individually.

I mean, move these many instances up to where the single instance used to be in the list

I see, that's not possible without hacking. That's because this file is autogenerated and the order is based on address offset.

elliotb-lowrisc · 2025-09-26T15:23:50Z

data/top_config.toml

 [[blocks]]
 name = "gpio"
-instances = 5 # RPi, Ard, Pmod0, Pmod1, PmodC
+instances = 6 # RPi, Ard, Pmod0, Pmod1, PmodC


Why is this being changed? I thought only five of the six GPIOs went through the pinmux

I think that this file should not only list IPs that relates to pinmux, but list all IP instances.

Then why does CI fail?

I guess it's because the manual changes that I have done in the RTL are wrong.

With @alees24 help, the test now pass. I should also test if the bitstream is correct

engdoreis · 2025-10-07T14:58:00Z

rtl/system/pinmux.sv

-  input  [31:0] gpio_ios_i   [GPIO_NUM],
-  input  [31:0] gpio_ios_en_i[GPIO_NUM],
+  output [31:0] gpio_ios_o   [5],
+  input  [31:0] gpio_ios_i   [5],


This change allows instances with direct ios (without going to pinmux). In this case we have 6 instances of gpio but only 5 goes to pinmux.

Don't add empty pin list to the block_io_to_pin_map dictionary. Signed-off-by: Douglas Reis <doreis@lowrisc.org>

The gpio was as declared in some places as having a single instance, but in other places it had 6 instances, but in the xbar it only had one instance. This commit makes it consistent. Signed-off-by: Douglas Reis <doreis@lowrisc.org>

engdoreis requested a review from elliotb-lowrisc September 26, 2025 14:53

engdoreis changed the title ~~[DRAFT] [rtl, gpio] Refactor gpio declaration~~ [DO NOT MERGE] [rtl, gpio] Refactor gpio declaration Sep 26, 2025

elliotb-lowrisc reviewed Sep 26, 2025

View reviewed changes

engdoreis force-pushed the gpio_refactor branch 2 times, most recently from 7b9135c to 82816d5 Compare October 7, 2025 14:56

engdoreis commented Oct 7, 2025

View reviewed changes

engdoreis force-pushed the gpio_refactor branch 4 times, most recently from 69156d0 to c6220a8 Compare October 8, 2025 16:07

engdoreis changed the title ~~[DO NOT MERGE] [rtl, gpio] Refactor gpio declaration~~ [rtl, gpio] Refactor gpio declaration Oct 8, 2025

engdoreis requested review from elliotb-lowrisc and marnovandermaas October 8, 2025 16:11

engdoreis marked this pull request as ready for review October 8, 2025 16:11

engdoreis force-pushed the gpio_refactor branch from c6220a8 to 4f34d60 Compare October 8, 2025 16:14

engdoreis requested a review from alees24 October 9, 2025 18:26

engdoreis added 3 commits November 4, 2025 17:51

[utils] Refactor the pin mapping scripts

f8e8fa0

Don't add empty pin list to the block_io_to_pin_map dictionary. Signed-off-by: Douglas Reis <doreis@lowrisc.org>

[util] Reduce the minimum space between blocks in the bus

fb71040

[rtl, gpio] Refactor the gpio instance declaration

31c0161

The gpio was as declared in some places as having a single instance, but in other places it had 6 instances, but in the xbar it only had one instance. This commit makes it consistent. Signed-off-by: Douglas Reis <doreis@lowrisc.org>

engdoreis force-pushed the gpio_refactor branch from 4f34d60 to 31c0161 Compare November 4, 2025 17:51

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

[rtl, gpio] Refactor gpio declaration#452

[rtl, gpio] Refactor gpio declaration#452
engdoreis wants to merge 3 commits intolowRISC:mainfrom
engdoreis:gpio_refactor

engdoreis commented Sep 26, 2025 •

edited

Loading

Uh oh!

elliotb-lowrisc left a comment

Uh oh!

elliotb-lowrisc Sep 26, 2025

Uh oh!

engdoreis Sep 30, 2025

Uh oh!

elliotb-lowrisc Sep 30, 2025

Uh oh!

engdoreis Oct 7, 2025

Uh oh!

elliotb-lowrisc Sep 26, 2025

Uh oh!

engdoreis Sep 30, 2025

Uh oh!

elliotb-lowrisc Sep 30, 2025

Uh oh!

engdoreis Oct 6, 2025

Uh oh!

engdoreis Oct 7, 2025

Uh oh!

engdoreis Oct 7, 2025 •

edited

Loading

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

2 participants

Conversation

engdoreis commented Sep 26, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

elliotb-lowrisc left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

engdoreis Oct 7, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

2 participants

engdoreis commented Sep 26, 2025 •

edited

Loading

engdoreis Oct 7, 2025 •

edited

Loading